1. Field of the Invention
The present invention relates to systems and methods capable of controlling multiple data access, and more particularly, to systems and methods capable of controlling multiple data access using a built-in timing generator.
2. Description of the Prior Art
In a fast-developing digital world where data systems are widely used, the accuracy and speed when performing data access, data transmission, data storage and data display have to be improved continuously. One of the most important factors that influence the performance of a data system is data access of the related memory devices. In addition, in a high-speed and multi-functional data system, different tasks are allotted to the memory devices so that corresponding processors and the memory devices can function properly. Common data systems can operate based on a synchronous data access structure or an asynchronous data access structure. In a synchronous data system, a synchronous clock is used for controlling the input/output signals of the memory devices and the internal control signals of the data system. Therefore, the synchronous data system can provide high-speed and accurate data accesses, as well as reduce the time for executing commands and transmitting data. On the other hand, an asynchronous data system does not require a synchronous clock for performing data access. Instead, data is stored or read when corresponding input signals or commands change.
The data systems become more and more complicated in order to provide more functions. Regardless of synchronous or asynchronous structures, a data system is often required to receive multiple commands given by different hosts. When receiving request commands given by different hosts, the data system has to adequately arrange the sequence for executing each request command so that each host can access data successfully. Since an asynchronous data system does not have a synchronous clock signal, an arbitration mechanism is required for prioritizing different request commands. Although a synchronous data system can arrange the sequence for executing each request command based on a synchronous clock signal having a constant period, transmitting the synchronous clock signal consumes large amount of power. In addition, multiple synchronous timing signals, instead of a single synchronous timing signal, are required in a complicated data system. When transmitting signal between the “time zones” of different synchronous timing signals, frequency and phase variations exist and request commands for transmitting signal asynchronously are also required. Therefore, in order to enhance system efficiency, lower power consumption and design data systems of larger scales, asynchronous data transmission without a synchronous timing signal becomes more and more important.
Reference is made to FIG. 1 for a functional diagram illustrating a prioritizing circuit 10 disclosed in U.S. Pat. No. 4,339,808 “ASYNCHRONOUS EVENT PRIORITIZING CIRCUIT”. The prioritizing circuit 10 includes a latch 12, a latch control 14, a priority logic 16, and a delay circuit 18. The latch 12 receives asynchronous request commands REQUEST1 and REQUEST2 respectively given by two hosts, and generates corresponding output signals Q1 and Q2 based on a strobe signal S sent from the latch control 14. Based on clear signals CLEAR1, CLEAR2 and the output signals Q1, Q2, the latch control 14 generates the strobe signal S and sends the strobe signal S to the latch 12 and the delay circuit 18. The delay circuit 18 generates a delayed strobe signal S′ corresponding to the strobe signal S, and sends the delayed strobe signal S′ to the priority logic 16. The priority logic 16 arbitrates priority between the output signals Q1 and Q2 and generates corresponding grant signals GRANT1 and GRANT2 based on the delayed strobe signal S′ generated by the delay circuit 18. The prior art prioritizing circuit 10 controls multiple data access using the delay circuit 18 whose characteristics tend to deviate from nominal values when the temperature or the operating voltages vary. Therefore, multiple data access may not be performed accurately and the correctly.
Reference is made to FIG. 2 for a functional diagram illustrating a control circuit 20 for asynchronous events disclosed in U.S. Pat. No. 6,591,323 “MEMORY CONTROLLER WITH ARBITRATION AMONG SEVERAL STROBE REQUESTS”. The control circuit 20 includes a pool/queue state machine SM1, transaction processor state machines SM2-SM4, bank state machines SM5-SM8, a command arbitrator 22, a command output flip flop 24, and a dynamic random access memory (DRAM) 26. The prior art control circuit 20 receives asynchronous request commands given by a plurality hosts via the pool/queue state machine SM1 and arbitrates priority between the plurality of request commands based on a state mechanism provided by the transaction processor state machines SM2-SM4 and the bank state machines SM5-SM8. Since a synchronous timing signal is required as the trigger signal in the state mechanism, the prior art control circuit 20 cannot be applied in asynchronous data systems.